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High Efficiency Audio Subsystem
ISL99203
The ISL99203 is a fully integrated high efficiency class-D mono amplifier combined with a capfree headphone amplifier. It is designed to maximize performance for mobile phone applications while saving valuable board space. The application circuit requires a minimum requirement of external components and operates from a 2.4V to 5.5V input supply. It is capable of delivering 1.5W of continuous output power with less than 10% THD+N driving a 8 load from a 5V supply. The speaker amplifier of the ISL99203 features a high-efficiency, low-noise modulation scheme. It operates with 85% efficiency at 400mW into 8 from 5V supply and has a signal-to-noise ratio (SNR) that is greater than 95dB. The architecture of the device allows it to achieve very low level pop and click. This minimizes voltage glitches at the output during turn-on and turn-off, thus reducing audible noise on activation and deactivation. EMI suppression is achieved by SRC (Slew Rate Control). The amplifier passes FCC Radiated Emissions Standards with 24 inches of Cable and achieves greater than 20dB margin under FCC limits. The class-D amplifier is designed to operate without a low pass output filer thus saving cost and board space. The headphone amplifier is a GND-reference capfree amplifier. It can output up to 35mW into 32 at 3.3V.
ISL99203
Features
* Operating Voltage 2.4V to 5.5V * Low Quiescent Current * Low Shutdown Current * Low RFI Susceptibility * Integrated Bypass Switch, I2C Controlled * I2C Control Interface * 40 Step Digital Volume Control * 3 Independent Volume Channels * 10 Distinct Output Modes * Speaker Amp Class-D * Protection for UV/TSD/OC * Independent Gain Boost for Headphone and Speaker * All Digital Interfaces 1.8V Compatible * Exposed Pad at Ground Voltage
Applications*(see page 16)
* Mobile Phones * PDAs * Portable Media Players * Portable Gaming
Ordering Information
PART NUMBER PART (Notes 1, 2, 3) MARKING ISL99203IIZ-T 203 NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free WLCSP and BGA packaged products employ special Pb-free material sets; molding compounds/die attach materials and SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL99203. For more information on MSL please see tech brief TB363. TEMP RANGE (C) PACKAGE (Pb-free) PKG. DWG. #
-40 to +85 20 Ball WLCSP W4x5.20
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL99203
Typical Application
8
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Block Diagram
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Pin Configurations
ISL99203 (20 BALL WLCSP) BOTTOM VIEW
SCL SDA GND_CPK RIN R_OUT 4
MO+ SWI+ GND_CP VDD_CP CN
ISL99203 (20 BALL WLCSP) TOP VIEW
R_OUT 4 CN 3 3 CP 2 2 L_OUT 1 1 LIN MI+ SWIMOVSS MIVDD_P GND_P VDD_CP GND_CP SWI+ MO+ RIN GND_CPK SDA SCL
GND_P
VDD_P
MI-
VSS
CP
MO-
SWI-
MI+
LIN
L_OUT
E
D
C
B
A
A
B
C
D
E
Pin Descriptions
20 BUMP CSP C4 A1 B2 A2 A3 A4 B4 B3 C3 D4 D3 E4 E3 D2 E2 E1 D1 C1 C2 B1 PIN NAME GND_CPK L_OUT VSS CP CN R_OUT RIN VDD_CP GND_CP SDA SWI+ SCL MO+ VDD_P GND_P MOSWIMI+ MILIN Charge-Pump Ground Left Headphone Out Negative-Power Supply Charge-Pump Cap + Charge-Pump Cap Right Headphone Out Right Input Channel Charge-Pump Power Supply Charge-Pump Ground I2C Data Switch Input + I2C Clock Mono O/P Positive Power Supply Power Ground Mono O/P Negative Switch Input Mono Positive Input Mono Negative Input Left input Channel PIN DESCRIPTION
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Absolute Maximum Ratings
(Reference to GND)
Thermal Information
Thermal Resistance (Typical, Note 4) JA (C/W) WLCSP Package . . . . . . . . . . . . . . . . . . . . . 71 Maximum Junction Temperature (Plastic Package). . . . . . . . . . . . . . . . . . . -65C to +150C Maximum Storage Temperature Range . . . -65C to +150C Dissipation Ratings Derating Factor 20 Balls 4x5 Array WLCSP . . . . . . . . . . . . . . .10.1mW/C Power Rating TA 20 Balls 4x5 Array WLCSP +25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.76W +70C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.12W +85C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.91W Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V LIN, RIN, MI+, MI -, SWI +, SWI - . . . . . -0.3V to VDD+0.3V ESD Ratings Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . 2kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 250V Charged Device Model . . . . . . . . . . . . . . . . . . . . . 1500V
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . -40C to +85C Operating Supply Voltage (VDD Pin). . . . . . . . . . 2.4V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
VDD = 3.6V. Typical Values Are Tested at VDD = 3.6V and the Ambient Temperature at +25C. All Maximum and Minimum Values Are Established Under the Recommended Operating Supply Voltage Range and Ambient Temperature, Unless Otherwise Noted. SYMBOL POUT TEST CONDITIONS Mono, RL = 8, THD = 1%, f = 1kHz, BTL, mode 1 Mono, RL = 8, THD = 10%, f = 1kHz, BTL, mode 1 Headphone out RL = 32, THD = 1%, f = 1kHz, mode 4 Headphone out RL = 32, THD = 10%, f = 1kHz, mode 4 MIN TYP MAX UNITS 740 925 47 62 mW mW mW mW
PARAMETER Output Power
Total Harmonic Distortion
THD+N
A-weighted, grounded inputs and output referred Mono, RL = 8, f = 1kHz, BTL, POUT = 500mW, mode 1 Headphone out, RL = 32, f = 1kHz, POUT = 50mW, mode 4 0.05 0.01 2 0.2 4.5 6.5 0.01 18 96 12.5 6 8 0.5 % % mV mV mA mA A dB dB k 400 kHZ dB dB dB dB
Output Offset Voltage
VOS
VIN = 0V, mode 1, Mono VIN = 0V, mode 4 Headphones
Quiescent Current
Iqq
O/P modes 2, 4, 6, VIN = 0V, no load O/P modes 1, 3, 5, 7, VIN = 0V, no load
Shutdown Current Digital Volume Control Range HP Mute Attenuation Input Impedance (Mono and HP) Average Switching Frequency Power Supply Rejection Ratio
ISD
Output mode 0 Max Gain
fSW
Output mode 1. VDD = 3.6V
250
325 75 85 61 66
PSRR-Mono VRIPPLE = 200mV, f = 217Hz, RL = 8, all inputs at GND, O/P mode 1 PSRR-HP VRIPPLE = 200mV, f = 217Hz, RL = 32, all inputs at GND, O/P mode 4 f = 217Hz, Vcm = 1VP-P, 0dB, mode 1, RL = 8 f = 217Hz, Vcm = 1VP-P, 0dB, mode 2, RL = 32
Common Mode rejection Ratio
CMRR
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Electrical Specifications
VDD = 3.6V. Typical Values Are Tested at VDD = 3.6V and the Ambient Temperature at +25C. All Maximum and Minimum Values Are Established Under the Recommended Operating Supply Voltage Range and Ambient Temperature, Unless Otherwise Noted. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER PROTECTION Thermal Shutdown Thermal Shutdown Hysteresis Overcurrent Shutdown
145 30
C C A mA 2.4 V ms
Mono
HP
1.3 200
Undervoltage Shutdown Wake-up Time from Shutdown NOISE PERFORMANCE Output Voltage Noise en Mono, mode 1 HP, mode 4, 7 33 12 tWU 3.5
V V
Electrical Specifications
VDD = 5V. Typical Values Are Tested at VDD = 5V and the Ambient Temperature at +25C. All Maximum and Minimum Values Are Established Under the Recommended Operating Supply Voltage Range and Ambient Temperature, Unless Otherwise Noted. TEST CONDITIONS Mono, RL = 8, THD = 1%, f = 1kHz, BTL, mode 1 Mono, RL = 8, THD = 10%, f = 1kHz, BTL, mode 1 Headphone out RL=32, THD = 1%, f = 1kHz, SE, mode 4 Headphone out RL=32, THD = 10%, f = 1kHz, SE, mode 4 MIN TYP 1 1.375 47 62 MAX UNITS W W mW mW
PARAMETER Output Power
SYMBOL POUT
Total Harmonic Distortion
THD+N
A-weighted, grounded inputs and output referred Mono, RL = 8, f = 1kHz, BTL, POUT = 500mW, mode 1 Headphone out, RL = 32, f = 1kHz, POUT = 50mW, mode 4 0.05 0.01 2 0.2 5 5.5 0.01 18 96 12.5 % % mV mV mA mA A dB dB k dB dB dB dB
Output Offset Voltage
VOS
VIN = 0V, mode 1, Mono VIN = 0V, mode 4 Headphones
Quiescent Current
Iqq
O/P modes 4 O/P modes 1
Shutdown Current Digital Volume Control Range HP Mute Attenuation Input Impedance (Mono and HP) Power Supply Rejection Ratio
ISD
Output mode 0 Max Gain
PSRRMono PSRR-HP
VRipple = 200mV, f = 217Hz, RL = 8, all inputs at GND, O/P mode 1 VRipple = 200mV, f = 217Hz, RL = 32, all inputs at GND, O/P mode 4, 7 f = 217Hz, Vcm = 1VP-P, 0dB, mode 1, RL = 8 f = 217Hz, Vcm = 1VP-P, 0dB, mode 2, RL = 32
75 85 61 66
Common Mode rejection Ratio
CMRR
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Electrical Specifications
VDD = 5V. Typical Values Are Tested at VDD = 5V and the Ambient Temperature at +25C. All Maximum and Minimum Values Are Established Under the Recommended Operating Supply Voltage Range and Ambient Temperature, Unless Otherwise Noted. (Continued) TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER PROTECTION Thermal Shutdown Thermal Shutdown Hysteresis Overcurrent Shutdown
SYMBOL
145 30
C C A mA 2.4 V ms
Mono
HP
1.3 200
Undervoltage Shutdown Wake-up time from Shutdown NOISE PERFORMANCE Output Voltage Noise en Mono, mode 1 HP, mode 4, 7 33 12 tWU 3.5
V V
SDA vs SCL Timing
tF SCL tSU:STA SDA (INPUT TIMING) tSU:DAT tHD:STA tHD:DAT tSU:STO tHIGH tLOW tR
tAA SDA (OUTPUT TIMING)
tDH
tBUF
TABLE 1. CHIP ADDRESS A7 Chip Address ID_ENB = 0 ID_ENB = 1 1 1 1 A6 1 1 1 A5 1 1 1 A4 1 1 1 A3 1 1 1 A2 0 0 0 A1 Pin Controlled 0 1 A0 0 0 0
TABLE 2. CONTROL REGISTERS D7 Mode Control Boost Control Mono Volume Control Extended Volume Control Left Volume Control Right Volume Control 0 0 1 1 1 1 D6 0 1 0 0 1 1 D5 0/1 1 0 1 0 1 D4 0 X MVC4 0 LVC4 RVC4 D3 X/MC3 Amp BYP MVC3 0 LVC3 RVC3 D2 MC2 GBM MVC2 RVC5 LVC2 RVC2 D1 MC1 GBHPL MVC1 LVC5 LVC1 RVC1 D0 MC0 GBHPR MVC0 MVC5 LVC0 RVC0
NOTE: GBM: Gain Boost on Mono Speaker; 0 = no boost, 1 = 3dB GBHP: Gain Boost on Headphone; 0 = no boost, 1 = 3dB Amp Bypass: 0 is no bypass (Switch OFF); 1 is bypass (Switch ON)
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TABLE 3. OUTPUT MODES OUTPUT MODE 0 1 2 3 4 5 6 7 10 14 MC3 0 0 0 0 0 0 0 0 1 1 MC2 0 0 0 0 1 1 1 1 0 1 MC1 0 0 1 1 0 0 1 1 1 1 MC0 0 1 0 1 0 1 0 1 0 0 SPEAKER OUTPUT SD GM x M SD 2 x (GL x L + GR x R) SD 2 x (GL x L + GR x R) + GM x M SD 2 x (GL x L + GR x R) 2 x (GL x L + GR x R) 2 x (GL x L + GR x R) RIGHT HP OUTPUT SD SD GM x M/2 SD GR x R SD GM x M/2 + GR x R GR x R GM x M/2 GM x M/2 + GR x R LEFT HP OUTPUT SD SD GM x M/2 SD GL x L SD GM x M/2 + GL x L GL x L GM x M/2 GM x M/2 + GL x L
NOTE: Power On Default Mode 0 0 0 0 M = Mono, Phone in R = RIN L = LIN SD = Shutdown GM = Mono Volume Control gain GR = Right HP Volume Control Gain GL = Left HP Volume Control gain TABLE 4. VOLUME CONTROL VOLUME STEP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VC4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 VC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 VC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN (dB) -82 -76 -70 -64.5 -58.5 -52 -46.5 -40.5 -34.5 -30 -26.5 -24 -21 -18 -15 -13.5 -11.5 -10 -8.5 -7 -6
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TABLE 4. VOLUME CONTROL (Continued) VOLUME STEP 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VC5 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 VC4 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VC3 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 VC2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VC1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VC0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN (dB) -4.5 -3 -1.5 0 1.5 3 4.5 6 7.5 9 10.5 12 12.75 13.5 14.25 15 15.75 16.5 17.25 18
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Typical Performance Characteristics
10.000 VDD = 5V LOAD = 8 + 68H 100.000 6kHz THD + N (%) 1kHz 0.100 20Hz 10.000 1.000 0.100 VDD= 4.2V 0.0100 0.001 0 VDD= 3.6V VDD= 3V VDD= 5V LOAD= 8 + 68H
THD + N (%)
1.000
0.010
0.001 0.00
0.20
0.40
0.60 0.80 1.00 OUTPUT POWER (W)
1.20
1.40 1.60
0.5
1.0
1.5
2.0
OUTPUT POWER (W)
FIGURE 1. TOTAL HARMORNIC DISTORTION PLUS NOISE vs POWER (MONO)
FIGURE 2. TOTAL HARMORNIC DISTORTION PLUS NOISE vs POWER (MONO)
10.000
VDD = 5V LOAD = 32
10.000 6kHz 1kHz THD + N (%) 1.000
VDD = 5V LOAD = 16 6kHz 20Hz
THD +N (%)
1.000
0.100 20Hz 0.010
0.100
1kHz
0.010
0.001 0.00
0.01
0.02 0.03
0.04 0.05
0.06 0.07 0.08
0.001 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 OUTPUT POWER (W)
OUTPUT POWER (W)
FIGURE 3. TOTAL HARMORNIC DISTORTION PLUS NOISE vs POWER (HEADPHONE)
FIGURE 4. TOTAL HARMORNIC DISTORTION PLUS NOISE vs POWER (HEADPHONE)
10.000
VDD = 3.7V LOAD = 32
10.000 6kHz THD + N (%) 1.000 20Hz 0.100 6kHz VDD = 3.7V LOAD = 16
THD + N (%)
1.000 20Hz 0.100
0.010
1kHz
0.010
1kHz
0.001 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 OUTPUT POWER (W)
0.001 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 OUTPUT POWER (W)
FIGURE 5. TOTAL HARMORNIC DISTORTION PLUS NOISE vs POWER (HEADPHONE)
FIGURE 6. TOTAL HARMORNIC DISTORTION PLUS NOISE vs POWER (HEADPHONE)
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Typical Performance Characteristics (Continued)
10.00 VDD = 3V LOAD = 32 THD+ N(%) 10.00 VDD = 3.7V LOAD = 32
THD+ N(%)
1.00
1.00
0.10
10mW
20mW
0.10
20mW
40mW
0.01 10
100
1k FREQUENCY (Hz)
10k
100k
0.01 10
100
1k FREQUENCY (Hz)
10k
100k
FIGURE 7. TOTAL HARMORNIC DISTORTION PLUS NOISE vs FREQUENCY (HEADPHONE)
FIGURE 8. TOTAL HARMORNIC DISTORTION PLUS NOISE vs FREQUENCY (HEADPHONE)
10.00
VDD = 3V LOAD = 16
10.00
VDD = 3.7V LOAD = 32
THD+ N(%)
THD+ N(%)
1.00 10mW 0.10 20mW
1.00
0.10
30mW
16mW
0.01 10
100
1k FREQUENCY (Hz)
10k
100k
0.01 10
100
1k FREQUENCY (Hz)
10k
100k
FIGURE 9. TOTAL HARMORNIC DISTORTION PLUS NOISE vs FREQUENCY (HEADPHONE)
FIGURE 10. TOTAL HARMORNIC DISTORTION PLUS NOISE vs FREQUENCY (HEADPHONE)
100.00
100.00 STEREO SINGLE-ENDED INPUTS OUT OF PHASE RL = 32, GAIN = 0dB THD +N (%) VDD = 2.5V STEREO SINGLE-ENDED INPUTS IN PHASE RL = 32, GAIN = 0dB VDD = 2.5V 1.00 VDD = 3.6V VDD = 5.0V
10.00 THD +N (%)
10.00
1.00
VDD = 3.6V
0.10
VDD = 5.0V
0.10
0.01 0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.01 0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
OUTPUT POWER (W)
OUTPUT POWER (W)
FIGURE 11. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
FIGURE 12. TOTAL HARMONIC DISTORTION + NOISE (HP) vs POWER
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Typical Performance Characteristics (Continued)
10 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 9 8 7 6 5 4 3 2.0 2.5 3.0 3.5 HEADPHONES MODE 4.0 4.5 5.0 5.5 SPEAKER MODE SPEAKER AND HEADPHONES MODE 100 STEREO SINGLE-ENDED INPUTS OUT OF PHASE RL = 16, GAIN = 0dB VDD = 2.5V 10 VDD = 3.6V VDD = 5.0V
1 0.1
VDD SUPPLY VOLTAGE (V)
1 10 Po TOTAL POWER (mW)
100
FIGURE 13. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 14. SUPPLY CURRENT (HEADPHONES) vs TOTAL OUTPUT POWER
100 SUPPLY CURRENT (mA)
500 SUPPLY CURRENT (mA) STEREO SINGLE-ENDED INPUTS OUT OF PHASE RL = 32, GAIN = 0dB 400 300 200 100
MONO INPUT MODE RL = 8 + 33H, GAIN = 6dB
10 VDD = 5.0V VDD = 3.6V
VDD = 2.5V
VDD = 2.5V
VDD = 5.0V
VDD = 3.6V 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 PO TOTAL OUTPUT POWER (W) 1.6
1 0.1
1 10 Po TOTAL POWER (mW)
100
FIGURE 15. SUPPLY CURRENT (HEADPHONES) vs TOTAL OUTPUT POWER
FIGURE 16. TOTAL POWER DISSIPATION (SPEAKER MODE) vs TOTAL OUTPUT POWER
OUTPUT POWER PER CHANNE (mW)
2.5 OUTPUT POWER (W) 2.0 1.5 1.0 0.5 0 2.0 THD + N = 10 % THD + N = 1% 2.5 3.0 3.5 4.0 4.5 5.0 5.5 MONO INPUT MODE RL = 8 + 33H, GAIN = 6dB
100 90 STEREO SINGLE-ENDED INPUT HEADPHONE R = 16, GAIN = 0dB OUT OF PHASE 80 L 70 60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 THD + N = 1% THD + N = 10%
SUPPLY VOLTAGE(V)
FIGURE 17. OUTPUT POWER (SPEAKER) vs SUPPLY VOLTAGE
FIGURE 18. OUTPUT POWER PER CHANNEL (HEADPHONE) vs SUPPLY VOLTAGE
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Typical Performance Characteristics (Continued)
OUTPUT POWER PER CHANNE (mW) 100 90 80 70 60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 THD + N = 1% STEREO SINGLE-ENDED INPUT HEADPHONE RL = 32, GAIN = 0dB OUT OF PHASE THD + N = 10% CROSSTALK (dB) SPEAKER MODE Rl = 8 + 33H -20 Po = 250mW -40 HEADPHONE RL = 32 -60 -80 -100 -120 -140 -160 10 100 1k FREQUENCY (Hz) SERIES1 10k 100k 0
FIGURE 19. OUTPUT POWER PER CHANNEL (HEADPHONE) vs SUPPLY VOLTAGE
FIGURE 20. SPEAKER TO HEADPHONE CROSSTALK vs FREQUENCY
0 -10 SPEAKER MODE, Rl = 8 + 33H VIN = 0.2VP-P, GAIN = 12dB -20 CMRR (dB) PSRR (dB) -30 -40 -50 -60 -70 -80 -90 -100 10 100 1k FREQUENCY (Hz) SERIES1 10k 100k
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 10
SPEAKER MODE RL = 8 + 33H
VDD = 2.6V VDD = 3.6V VDD = 5.0V 100 1k FREQUENCY (Hz) 10k 100k
FIGURE 21. COMMON-MODE REJECTION RATIO vs FREQUENCY
FIGURE 22. POWER SUPPLY REJECTION RATIO (SPEAKER) vs FREQUENCY
0 -10 STEREO SINGLE-ENDED -20 INPUT HP MODE RL = 32 -30 -40 -50 -60 -70 VDD = 2.5V -80 -90 -100 VDD = 5.0V -110 VDD = 3.6V -120 10 100 1k 10k 100k FREQUENCY (Hz)
FIGURE 23. POWER SUPPLY REJECTION RATIO (HEADPHONES) vs FREQUENCY
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PSRR (dB)
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Typical Performance Characteristics (Continued)
SDA SDA
SPEAKER OUTPUT
SPEAKER OUTPUT
FIGURE 24. SPEAKER OUTPUT - START-UP
FIGURE 25. SPEAKER OUTPUT - SHUTDOWN
SDA
SDA
HEADPHONE OUTPUT
HEADPHONE OUTPUT
FIGURE 26. HEADPHONE OUTPUT - START-UP
FIGURE 27. HEADPHONE OUTPUT - SHUTDOWN
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Theory of Operation
The ISL99203 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL99203 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 28). A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 29). The ISL99203 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL99203 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation.
Protocol Conventions
Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 28). On power-up of the ISL99203, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL99203 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 29). A START condition is ignored during the power-up of the device.
SCL
SDA
START
DATA STABLE
DATA DATA CHANGE STABLE
STOP
FIGURE 28. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER START
HIGH IMPEDANCE
ACK
FIGURE 29. ACKNOWLEDGE RESPONSE FROM RECEIVER
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 12/17/09 REVISION FN7547.0 Initial release. CHANGE
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL99203 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN7547.0 December 17, 2009
ISL99203
Package Outline Drawing
W4x5.20
4x5 Array 20 Ball Wafer Level Chip Scale Package (WLCSP) Rev 1 8/09
2.545 0.02
X
2.00
Y
20X 0.32 0.03 4 0.25 3
2.045 0.02 2 1
0.10
1.50
0.50
E
PIN 1 (A1 CORNER)
TOP VIEW
D
C 0.50
B
A
(4X)
BOTTOM VIEW
0.33
PACKAGE OUTLINE 0.30 0.015
3 0.025 BSC
0.23 0.015
0.10 M Z X Y 0.05 M Z
0.32 0.03
Z
SEATING PLANE
0.05 Z
0.28
0.50
SIDE VIEW
4 NSMD
TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994, and JESD 95-1 SPP-10. 3. 4. Back side coat 0.25mm thick applied to CSP package top. NSMD refers to non-solder mask defined pad design per Intersil tech brief www.intersil.com/data/tb/TB451.pdf
17
FN7547.0 December 17, 2009

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